BVdss only specifies the voltage threshold. For turn-off events, you still need to verify the voltage spike and avalanche energy.

When an inductive load is turned off, the current cannot drop to zero instantly. Parasitic inductance will raise the drain voltage; if the freewheeling or clamping path is insufficient, the MOS will enter avalanche mode and dissipate the stored energy in its junction region. A bus voltage lower than the rated withstand voltage only means there is sufficient margin in steady state, and it cannot guarantee that the peak value and energy of each turn-off operation are safe.

For a 48V bus with a 100V MOS, the steady-state VDS is only over 40V, which seems to leave plenty of withstand voltage margin. However, when a motor, relay or long-line load is turned off, the device still occasionally suffers short-circuit failure, and a narrow but high drain spike can be observed on the oscilloscope. The clear conclusion is: static voltage margin cannot replace the turn-off energy verification.

At the moment of turn-off, the load inductance, wiring harness and loop parasitic inductance all maintain the original current. If there is no controlled path for the energy to be released, VDS will be raised, and even push the MOS into avalanche. This article only focuses on this failure chain, and will not combine issues like gate mis-turn-on, thermal design and short-circuit protection into one piece.

What exactly does the rated withstand voltage prove?

The BVdss in the datasheet is a breakdown index measured under specified gate-source voltage, drain current and temperature conditions. It tells you the approximate threshold for the device to transition from the blocking region to the breakdown region, but it does not mean that the device can absorb energy near this voltage indefinitely.

The actual turn-off waveform also includes bus voltage, layout parasitics, inductor stored energy, diode recovery and clamping actions. As long as the spike exceeds the threshold for a short time, the MOS may bear the avalanche current; whether it will be damaged depends on the single-event energy, pulse width, initial junction temperature and number of repetitions.

Figure 1 Turn-off loop of VBUS, LLOAD, Q1 and DCLAMP

BVdss is a voltage boundary, not a pass for all avalanche pulses.

How is the drain spike raised by the inductor?

The voltage across the inductor is related to the rate of change of current. When the MOS is turned off quickly, the current tends to continue flowing in its original direction; if the freewheeling diode, TVS, RCD or active clamp has not taken over, the loop will raise the drain voltage to a level high enough to find the next conduction path.

The probe connection method directly affects the observed spike. A long ground wire forms an extra loop, which may not only pick up magnetic fields, but also misplace the measurement reference. You should use a short return path or compliant differential measurement, and record VDS and ID at the same time, to avoid calculating energy only based on a single high-spike curve.

Figure 2 Synchronous trigger waveforms of VDS and ID when Q1 is turned off

Why can’t avalanche energy be judged only by a single event?

The single-event avalanche capability usually corresponds to a specified inductor, current, junction temperature and test circuit. Periodic PWM, frequent relay operations or fault retries will subject the device to repeated shocks, and the average temperature rise and local junction temperature accumulation are different from those in a single test.

Figure 3 Layout review of clamping devices, power loops and test points

Device batches, temperature and parallel current sharing will also change the actual stress. When two MOSs are connected in parallel, the static on-state current may be balanced, but the current may not be evenly distributed during the avalanche moment. Dividing the total energy by the number of devices cannot automatically yield a reliable conclusion.

• Single-event boundary: Verify EAS, initial current and junction temperature conditions.
• Repetitive boundary: Verify frequency, thermal accumulation and device lifetime.
• Current sharing boundary: Do not assume that energy is evenly distributed among parallel devices.

How to find a truly effective clamp with a single variable?

Keep the bus voltage, load inductance, turn-off current and gate resistance unchanged, and only modify the freewheeling or clamping branch. Compare the VDS peak value, clamping duration, ID decay, MOS temperature rise and clamping device temperature rise; when the spike decreases but the duration increases significantly, the energy still needs to be recalculated.

Figure 4 VDS energy comparison between the baseline and the clamped variable

The clamping device should be placed close to the loop to be limited, and connected to a clear reference node. The parasitic inductance of long traces will create an extra difference between the TVS’s rated voltage and the actual peak value of the MOS. The measurement point should also be located at the drain-source terminal of the MOS, not at the remote bus connector.

1. Fix the turn-off current to ensure consistent stored energy in the two tests.
2. Measure VDS and ID synchronously, and the integration window should cover the complete pulse.
3. Review the thermal boundary to cover repeated operations and high-temperature starting conditions.

When should you not rely on the MOS avalanche to withstand stress passively?

When the load energy is large, the operation is frequent, the ambient temperature is high, or the failure consequence is serious, you should prioritize providing a clear freewheeling and clamping path, instead of taking the avalanche capability as a normal operating mode. The avalanche parameters are more suitable as an abnormal margin, and the specific application should be subject to the description of the target device.

If the turn-off spike comes from high-frequency ringing caused by the package and extremely short traces, you need to distinguish it from the slow energy release of the load inductor. The two may overlap on the same VDS waveform, but their processing methods are different. First separate them according to the time scale and current path, and avoid using a large TVS to cover all phenomena.

Reliable turn-off requires the stored energy to have a controlled path, and leave sufficient margin for the MOS’s peak voltage, avalanche energy and junction temperature at the same time.

Conclusion

A bus voltage lower than the MOS withstand voltage only proves that the steady-state threshold is not exceeded. Zoom in on the VDS and ID waveforms during the short turn-off period, and you will know whether the device is absorbing energy for the entire loop.

If the spike position, duration and load current do not match, correct the measurement loop first, then discuss clamping; incorrect waveforms will lead the component selection in the wrong direction.

Does your VDS spike occur at the turn-off edge, the moment when the diode takes over, or during a slow decay period after the load is disconnected?

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