With the rapid advancement of technology, the demand for high-temperature-resistant integrated circuits (ICs) in commercial, industrial, and automotive sectors continues to soar. High-temperature environments can severely constrain the performance, reliability, and safety of integrated circuits, necessitating innovative technological solutions to overcome related technical challenges. This article aims to explore the impact of high temperatures on integrated circuits, introduce the challenges posed by high junction temperatures, and provide design techniques suitable for high-power applications to address these challenges.
Challenges Posed by High Junction Temperatures
Semiconductor devices operating at elevated temperatures experience reduced circuit performance and shortened lifespans. For silicon-based semiconductors, transistor parameters decline with increasing temperature, with the upper limit falling below 300°C due to the influence of intrinsic carrier density. Devices relying on selective doping may fail or exhibit poor performance.
The primary technical challenges affecting IC operation at high temperatures include:
- Increased leakage current
- Reduced MOS transistor threshold voltage
- Decreased carrier mobility
- Heightened sensitivity to latch-up effects
- Accelerated degradation mechanisms
- Challenges to packaging and bonding reliability
To design ICs capable of operating at high temperatures, it is crucial to understand the challenges faced under such conditions. The following sections will delve into the challenges confronting IC design.
- Increased Leakage Current
The increase in leakage current in CMOS circuits primarily stems from elevated semiconductor PN junction leakage and subthreshold channel leakage.
▷ Reverse-Biased PN Junction Leakage
At higher temperatures, increased thermal energy in semiconductors leads to the generation of more electron-hole pairs, resulting in higher leakage currents. Junction leakage depends on doping levels and typically grows exponentially with temperature. According to a widely used rule of thumb, junction current roughly doubles for every 10°C increase in temperature.
The leakage current of a diode comprises drift current and diffusion current:
Where q is the elementary charge of an electron, Aj is the junction area, ni is the intrinsic carrier concentration, W is the depletion region width, τ is the effective minority carrier lifetime, L is the diffusion length, and N is the doping density in the neutral region.
At moderate temperatures, leakage current is primarily caused by thermal generation of electron-hole pairs in the depletion region. At high temperatures, leakage current is mainly caused by minority carriers generated in the neutral region. Drift current is proportional to the depletion region width, implying it is proportional to the square root of the junction voltage (under normal reverse voltage), while diffusion current is independent of junction voltage and inversely proportional to doping density N. Higher doping levels result in less diffusion leakage at temperatures above approximately 150°C.
The exponential increase in leakage current affects most active devices (such as bipolar transistors, MOS transistors, diodes) and some passive devices (such as diffusion capacitance, resistors). However, devices isolated by oxides, such as polysilicon resistors, polysilicon diodes, poly-poly capacitors, and metal-metal capacitors, are not affected by junction leakage. Junction leakage is considered the most severe challenge in high-temperature bulk CMOS circuits.
▷ Subthreshold Channel Leakage
When a MOS transistor is turned off, the gate-source voltage VGS is typically set to zero. Due to the non-zero drain-source voltage VDS, a small current flows between the drain and source. Subthreshold leakage occurs when Vgs is below the threshold voltage Vt, i.e., in the subthreshold or weak inversion region. The drain-source current in this region is not zero but exponentially related to Vgs, primarily due to minority carrier diffusion.
This current is highly dependent on temperature, process, transistor size, and type. Short-channel transistors exhibit increased current, while transistors with higher threshold voltages show decreased current. The subthreshold slope factor S describes how effectively a transistor switches from off (low current) to on (high current) and is defined as the change in VGS required to change the drain current by a factor of ten:
Where n is the subthreshold slope coefficient (typically around 1.5). For n = 1, the slope factor is 60mV/decade, meaning the drain current decreases by a factor of ten for every 60mV below the threshold voltage Vt. A typical n = 1.5 implies a slower current decrease, at 90mV/decade. To effectively turn off a MOS transistor and reduce subthreshold leakage, the gate voltage must drop sufficiently below the threshold voltage.
▷ Gate Oxide Tunneling Leakage
For extremely thin gate oxides (thickness below approximately 3 nanometers), the impact of tunneling leakage current must be considered. This current is temperature-dependent and triggered by multiple mechanisms. Fowler-Nordheim tunneling occurs when electrons traverse the triangular potential barrier formed by the oxide under high electric fields. As the effective barrier height decreases, tunnel current increases with temperature. Higher temperatures also enhance trap-assisted tunneling, where electrons pass through intermediate trap states in the oxide. For ultrathin oxides, direct tunneling becomes significant, with tunneling probability rising due to increased electron thermal energy.
- Reduced Threshold Voltage
The threshold voltage Vt of a MOS transistor is closely related to temperature and typically decreases linearly with increasing temperature. This is due to factors such as increased intrinsic carrier concentration, narrowing of the semiconductor bandgap, changes in surface potential at the semiconductor-oxide interface, and decreased carrier mobility. The decrease in threshold voltage caused by temperature rise leads to an exponential increase in subthreshold leakage current.
- Decreased Carrier Mobility
Carrier mobility directly affects MOS transistor performance and is influenced by lattice scattering and impurity scattering. As temperature rises, lattice vibrations (phonons) intensify, leading to more frequent scattering of charge carriers and decreased mobility. Additionally, higher temperatures increase intrinsic carrier concentration, triggering more carrier-carrier scattering and further reducing mobility. When the temperature rises from 25°C to 200°C, carrier mobility roughly halves.
Carrier mobility significantly impacts several key MOS parameters. Decreased carrier mobility reduces drive current, slows transistor switching speed, and degrades overall performance. Higher on-resistance increases power loss and reduces efficiency. Lower mobility also decreases transconductance, slows subthreshold slope (increasing subthreshold leakage), reduces carrier saturation velocity (crucial for short-channel devices), and indirectly affects threshold voltage.
- Heightened Sensitivity to Latch-Up Effects
Isolation between diodes, transistors, and other components in integrated circuits is achieved through reverse-biased P-N junctions. During circuit development, precautions must be taken to ensure these junctions reliably block under expected application conditions. These P-N junctions form N-P-N and P-N-P structures with adjacent junctions, creating parasitic NPN or PNP transistors that may be inadvertently activated.
Latch-up occurs in CMOS ICs when parasitic PNP and NPN bipolar transistors interact, forming a low-impedance path between power rails and ground. This creates a silicon-controlled rectifier (SCR) with positive feedback, leading to excessive current flow and potential permanent device damage. Figure 1 shows a cross-sectional layout of a standard CMOS inverter, including parasitic NPN and PNP transistors. Under normal operation, all junctions are reverse-biased.
Figure 1. Cross-sectional view of an inverter with labeled parasitic bipolar transistors and schematic of parasitic bipolar transistors
Latch-up activation primarily depends on the β values of parasitic NPN and PNP transistors, as well as N-well, P-well, and substrate resistances. As temperature rises, the DC current gain (β) of bipolar transistors and the resistance of wells and substrates also increase.
Under high-temperature conditions, increased latch-up sensitivity can also be viewed as a decrease in the threshold voltage of bipolar junction transistors (BJTs), making it easier to generate a voltage drop across well and substrate resistances sufficient to activate parasitic bipolar transistors. The base-emitter voltage decreases by approximately -2mV/°C with temperature. When the temperature rises from 25°C to 200°C, the base-emitter voltage decreases by 350mV. With a typical room-temperature threshold voltage of 0.7V, this means the threshold voltage roughly halves.
- Accelerated Degradation Mechanisms
Arrhenius’s law is widely used in reliability engineering to model the impact of temperature on the failure rate of materials and components.
Where R(T) is the rate constant, Ea is the activation energy, k is the Boltzmann constant (8.617 · 10−5 eV/K), and T is the absolute temperature (in Kelvin). Typically, reliability halves for every 10°C increase in temperature.
▷ Time-Dependent Dielectric Breakdown (TDDB)
TDDB is a failure mechanism in electronic devices where dielectric materials (such as the gate oxide in MOS transistors) degrade over time due to prolonged exposure to electric fields, leading to increased leakage current. When voltage prompts the flow of high-energy electrons, conductive paths form within the oxide, along with traps and defects. When these conductive paths cause a short circuit in the oxide, the dielectric layer fails. The failure time TF decreases exponentially with increasing temperature.
▷ Negative/Positive Bias Temperature Instability (NBTI/PBTI)
NBTI affects p-channel MOS devices operating with negative gate-source voltages, while PBTI affects NMOS transistors in the accumulation region. Under gate bias, defects and traps increase, leading to elevated threshold voltage, reduced drain current, and decreased transconductance. This degradation exhibits logarithmic time dependence and exponential temperature increase, with partial recovery above 125°C.
▷ Electromigration
Electromigration refers to the gradual displacement of metal atoms in conductors due to current flow, forming voids and hillocks. Thus, if voids formed in metal lines are large enough to sever them, it can lead to open circuits; if these protrusions extend sufficiently to bridge the affected metal with an adjacent one, it can cause short circuits. Electromigration accelerates with increasing current density and temperature, especially after void formation, leading to current crowding and localized heating. The probability of metal line failure increases exponentially with temperature, quadratically with current density, and linearly with wire length. Copper interconnect devices can withstand approximately five times the current density of aluminum while maintaining similar reliability.
▷ Hot Carrier Degradation
Hot carrier degradation occurs when channel electrons accelerate in high electric fields near the drain of MOS transistors. Interface states, traps, or holes are generated in the gate oxide. It affects parameters such as threshold voltage VT, current gain β, on-resistance RDS_ON, and subthreshold leakage. At higher temperatures, the mean free path decreases, reducing the energy gained by carriers and making hot carrier degradation more significant at lower temperatures.
OMAGINE specializing in ODM PCB design, PCB assembly, open source hardware related modules and sourcing service.
