01 Power Supply Layout and Wiring

Digital circuits often require discontinuous current, which can generate surge currents in some high-speed devices.

If the power wiring is long, the presence of surge currents can lead to high-frequency noise, which can be introduced into other signals. High-speed circuits inevitably have parasitic inductance, parasitic resistance, and parasitic capacitance, so this high-frequency noise will ultimately couple into other circuits. The presence of parasitic inductance also reduces the ability of the wiring to withstand maximum surge currents, resulting in some voltage drop that may disable the circuit.

Therefore, it is particularly important to add bypass capacitors in front of digital devices. Larger capacitors are limited in energy transfer rate, so a combination of a large and a small capacitor is usually used to cover the full frequency range.

Avoiding Hotspots: Signal vias create voids in the power plane and bottom layer. Improper placement of vias can increase current density in certain areas of the power or ground plane, known as hotspots.

To avoid this, we should strive to prevent such situations when setting vias, to avoid splitting the plane and ultimately causing EMC issues.

The best way to avoid hotspots is usually to place vias in a mesh pattern, which ensures uniform current density and prevents the plane from being isolated, keeping the return path short and avoiding EMC issues.

02 Bending of Wiring

When routing high-speed signal lines, bending should be avoided as much as possible. If bending is unavoidable, use obtuse angles instead of sharp or right angles.

When routing high-speed signal lines, we often achieve equal length by routing in a serpentine pattern, which is also a form of bending. The line width, spacing, and bending method should be selected reasonably, with spacing satisfying the 4W/1.5W rule.

03 Signal Proximity

If high-speed signal lines are too close, crosstalk can easily occur. Sometimes, due to layout, board frame size, or other reasons, the distance between high-speed signal lines exceeds our minimum requirements. In such cases, we can only try to increase the distance between high-speed signal lines near their bottlenecks.

If space permits, increase the distance between two high-speed signal lines as much as possible.

04 Wiring Stubs

Long stubs act like antennas and can cause serious EMC issues if not handled properly.

Stubs can also cause reflections, reducing signal integrity. Stubs are most commonly created when pull-up or pull-down resistors are added to high-speed signal lines, and they can be minimized by using a daisy-chain wiring pattern.

Experience shows that if the length of a stub is greater than 1/10 of the wavelength, it can act as an antenna and become a problem.

05 Impedance Discontinuities

The impedance of a trace generally depends on its width and the distance between it and the reference plane. Wider traces have lower impedance. The same principle applies to the pads of interface terminals and devices.

When a pad of an interface terminal is connected to a high-speed signal line, if the pad is particularly large and the signal line is particularly narrow, the large pad will have low impedance, while the narrow trace will have high impedance. In this case, impedance discontinuity will occur, causing signal reflection.

To solve this problem, a copper-free zone is usually placed under the large pad of the interface terminal or device, and the reference plane for the pad is placed on another layer to increase impedance and maintain impedance continuity.

Vias are another source of impedance discontinuity. To minimize this effect, unnecessary copper should be removed from the inner layers connected to the vias.

This operation can be performed during design using CAD tools or by communicating with the PCB manufacturer to remove unnecessary copper and ensure impedance continuity.

06 Differential Signals

For high-speed differential signal lines, we must ensure equal width and spacing to achieve a specific differential impedance value. Therefore, try to ensure symmetry when routing differential signal lines.

Avoid placing vias or components within differential pairs, as this can cause EMC issues and impedance discontinuities.

Sometimes, high-speed differential signal lines need to be connected in series with coupling capacitors. These capacitors should also be arranged symmetrically, and their packages should not be too large. 0402 packages are recommended, 0603 packages are acceptable, and packages larger than 0805 or side-by-side capacitors should not be used.

Vias can cause significant impedance discontinuities, so try to minimize their use in high-speed differential signal pairs. If vias are necessary, arrange them symmetrically.

07 Equal Length

For some high-speed signal interfaces, such as buses, we need to consider the arrival time and time delay error between individual signal lines. For example, in a set of high-speed parallel buses, the arrival time of all data signal lines must be within a certain time delay error to ensure consistency in setup and hold times. To meet this requirement, we must consider equal length routing.

High-speed differential signal pairs must have strict time delays; otherwise, communication may fail. To meet this requirement, serpentine patterns can be used to achieve equal length and satisfy time delay requirements.

Serpentine patterns should generally be placed at the source of length mismatches, not at the far end. Placing them at the source ensures that the positive and negative signals of the differential pair are transmitted synchronously for most of the time.

Wiring bends are one of the sources of length mismatches. To achieve equal length at bends, the compensation should be close to the bend (<=15mm).

If there are two bends with a distance of <15mm between them, their length mismatches will compensate for each other, so no additional equalization is required.

For different sections of high-speed differential signal lines, equal length should be maintained independently. Vias, series coupling capacitors, and interface terminals can divide high-speed differential signal lines into two parts, so special attention should be paid to this.

Ensure equal length separately because many EDA software only focus on whether the entire trace has length mismatches during DRC.

For interfaces such as LVDS display devices, there will be multiple differential pairs with strict timing requirements and small time delays between them. Therefore, for such differential signals, we require compensation within the same plane because signal transmission speeds can differ between layers.

Some EDA software includes the internal wiring of pads in the length calculation. If length compensation is performed at this time, the actual result will have length mismatches. Therefore, special attention should be paid when using some EDA software.

Whenever possible, choose symmetrical routing to avoid the need for serpentine patterns to achieve equal length.

If space permits, try to add a small loop at the source of the short differential line for compensation instead of using a serpentine pattern.